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1 chip codec s5t8554b/7b 1 introduction the s5t8554b/7b are single-chip pcm encoders and decoders (pcm codecs) and pcm line filters. these devices provide all the functions required to interface a full-duplex voice telephone circuit with a time-division-multiplex (tdm) system. these devices are designed to perform the transmit encoding and receive decoding as well as the transmit and receive filtering functions in pcm system. they are intended to be used at the analog termination of a pcm line or trunk. these devices provide the bandpass filtering of the analog signals prior to encoding and after decoding. these combination devices perform the encoding and decoding of voice and call progress tones as well as the signalling and supervision information. features ? complete codec and filtering system ? meets or exceeds at&t d3/d4 and ccitt specifications m -law: s5t8554b, a-law: s5t8557b ? on-chip auto zero, sample and hold, and precision voltage references ? low power dissipation: 60mw (operating), 3mw (standby) ? 5v operation ? ttl or cmos compatible ? automatic power down ordering information device package operating temperature s5t8554b02-l0b0 s5t8557b02-l0b0 16-cerdip - 25 c to 125 c s5t8554b01-d0b0 S5T8557B01-D0B0 16-dip-300a - 25 c to +70 c s5t8554b01-s0b0 s5t8557b01-s0b0 16-sop-bd300 - 25 c to +70 c 16-cerdip 16-dip-300a 8 - dip - 300
s5t8554b/7b 1 chip codec 2 pin configuration pin discription pin no symbol description 1 v bb v bb = - 5v 5% 2 gnda analog ground. 3 vf r o analog output of the receive power amp. 4 v cc v cc = +5 v 5% 5 fs r receive frame sync pulse. 8khz pulse train 6 d r pcm data input. 7 blck r / clksel logic input which selects either 1.536mhz/1.544mhz or 2.048mhz for master clock in normal operation and bclk x is used for both tx and rx directions. alternately direct clock input available, vary from 60khz to 2.048mhz. 8 mclk r / pdn when mclk r is connected continuously high, the device is powered down. normally connected continuously low, mclk x is selected for all dac timing. alternately direct 1.536mhz/1.544mhz or 2.048mhz clock input available. 9 mclk x must be 1.536mhz/1.544mhz or 2.048mhz. 10 blck x may be vary from 64khz to 2.048mhz but bclk x is externally tied with mclk x in normal operation. 11 d x pcm data output. 12 fs x tx frame sync pulse. 8khz pulse train. 13 ts x changed from high to low during the encoder timeslot. open drain output. 14 gs x analog output of the tx input amplifier. used to set gain through external resistor. 15 vf x i - inverting input stage of the tx analog signal. 16 vf x i + non-inverting input stage of the tx analog signal. vf x i + vf x i - gs x ts x fs x s d x bclk x mclk x v bb gnda vf r o v cc fs r d r bclk r /clksel mclk r /pdn 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 kt8554/7 s5t8554b/7b
1 chip codec s5t8554b/7b 3 absolute maximum rating electrical characteristics (unless otherwise noted, v cc = 5.0v 5%, v bb = - 5.0v 5%, gnd a = 0v, ta = 0 c to 70 c; typical characteristics specified at v cc = 5.0v, v bb = - 5.0v, ta=25 c; all signals referenced to gnd a ) characteristic symbol value unit positive supply voltage v cc 7 v negative supply voltage v bb - 7 v voltage at any analog input or output v i (a) v cc + 0.3 ~ v bb - 0.3 v voltage at any digital input or output v i (d) v cc + 0.3 ~ gnd a - 0.3 v operating temperature range ta - 25 ~ +125 c storage temperature range t stg - 65 ~ +150 c lead temperature (soldering, 10 secs) t lead 300 c characteristic symbol test conditions min. typ. max. unit power dissipation power-down current i cc (down) no load - 0.5 1.5 ma power-down current i bb (down) no load - 0.05 0.3 ma active current i cc (a) no load - 6.0 9.0 ma active current i bb (a) no load - 6.0 9.0 ma digital interface input low voltage v il - - - 0.6 v input high voltage v ih - 2.2 - - v input low current i il gnd a v in v il , all digital input - 10 - 10 m a input high current i ih v ih v in v cc - 10 - 10 m a output low voltage v ol d x , i l = 3.2ma sig r , i l = 1.0ma ts x , i l = 3.2ma, open drain - - 0.4 0.4 0.4 v v v output high voltage i o (hz) d x , i h = - 3.2ma sig r , i h = - 1.0ma 2.4 2.4 - - v v output current in high impedance state (tri -state) i o (hz) d x , gnd a v o v cc - 10 - 10 m a analog interface with receive filter output resistance r o pin vf r o - 1 3 w
s5t8554b/7b 1 chip codec 4 electrical characteristics (unless otherwise noted, v cc = 5.0v 5%, v bb = - 5.0v 5%, gnd a = 0v, ta = 0 c to 70 c; typical characteristics specified at v cc = 5.0v, v bb = - 5.0v, ta=25 c; all signals referenced to gnd a ) characteristic symbol test conditions min. typ. max. unit load resistance r l vf r o = 2.5v 600 - - w load capacitance c l - - - 500 pf output dc offset voltage v oo (rx) - - 200 - 200 mv analog interface with transmit input amplifier input leakage current i lkg -2.5v v +2.5v, vf x i+ or vf x i- - 200 - 200 na input resistance r i -2.5v v +2.5v, vf x i+ or vf x i- 10 - - m w output resistance r o closed loop, unity gain - 1 3 w load resistance r l gs x 10 - - k w load capacitance c l gs x - - 50 pf output dynamic range v od (tx) gs x , r l 10kw 2.8 - - v voltage gain g v vf x i+ to gsx 5,000 - - v/n unity gain bandwidth bw - 1 2 - mhz offset voltage v io (tx) - - 20 - 20 mv common-mode voltage v cm (tx) cmrrxa > 60db - 2.5 - 2.5 v common-mode rejection ratio cmrr dc test 60 - - db power supply rejection ratio psrr dc test 60 - - db
1 chip codec s5t8554b/7b 5 timing characteristics (unless otherwise noted, v cc = 5.0v 5%, v bb = - 5.0v 5%, gnd a = 0v, ta = 0 c to 70 c; typical characteristics specified at v cc = 5.0v, v bb = - 5.0v, ta=25 c; all signals referenced to gnd a ) characteristic symbol test conditions min. typ. max. unit frequency of master clock f mck depends on the device used and the bclk r /clksel pin. mclk x and mclk r - 1.536 1.544 2.048 - ns rise time of bit clock t r (bck) t pb = 488ns - - 50 ns fall time of bit clock t f (bck) t pb = 488ns - - 50 ns holding time from bit clock low to frame sync t h (lfs) long frame only 0 - - ns holding time from bit clock high to frame sync t h (rfs) short frame only 0 - - ns set-up time from frame sync to bit clock low t su (fbcl) long frame only 80 - - ns delay time from bclk x high to data valid t d (hdv) load = 150pf plse 2 lsttl loads 0 - 180 ns delay time to ts x low t d (tsxl) load = 150pf plse 2 lsttl loads - - 140 ns delay time from bclk x low to data output disabled t d (ldd) - 50 - 165 ns delay time to valid data from fsx or bclk x , whichever comes later t d (vd) c l = 0pf to 150pf 20 - 165 ns set-up time from d r valid to bclk r/x low t su (drbl) - 50 - - ns hold time from fs r/x low to d r invalid t h (bldr) - 50 - - ns set-up time from fs r/x to bclk r/x low t su (fbls) short frame sync pulse (1 or 2 bit clock periods long) (note 1) 50 - - ns width of master clock high t w (mckh) mclk x and mclk r 160 - - ns width of master clock low t w (mckl) mclk x and mclk r 160 - - ns rise time of master clock t r (mck) mclk x and mclk r - - 50 ns fall time of master clock t f (mck) mclk x and mclk r - - 50 ns set-up time from bclk x high (and fs x in long frame sync mode) to mclk x falling edge t su (bhmf) first bit clock after the leading edge fs x - - - -
s5t8554b/7b 1 chip codec 6 timing characteristics (unless otherwise noted, v cc = 5.0v 5%, v bb = - 5.0v 5%, gnd a = 0v, ta = 0 c to 70 c; typical characteristics specified at v cc = 5.0v, v bb = - 5.0v, ta=25 c; all signals referenced to gnd a ) note: for short frame sync timing, fs x and fs r must go high while their respective bit clocks are high. characteristic symbol test conditions min. typ. max. unit period of bit clock t ck - 485 488 15,725 ns width of bit clock high t w (bckh) v ih = 2.2 160 - - ns width of bit clock low t w (bckl) vil = 0.6v 160 - - ns hold time from bclk x/r low to fs x/r low t h (blfl) short frame sync pulse (1 or 2 bit clock periods long) (note 1) - - - ns hold time from 3rd period of bit clock low to frame sync (fs x or fs r ) t h (3rd) long frame sync pulse (from 3 to 8 bit clock periods long) 100 - - ns minimum width of the frame sync pulse (low level) t wfl 64k bit/s operating mode - - - ns
1 chip codec s5t8554b/7b 7 timing diagram figure 1. short frame sync timing 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 tsx t r(mck) mclk r mclk x bclk x fs x d x bclk r fs r d r t d(tsxl) t f(mck) t w(mck) t ck t su(bhmf) t w(mckh) t h(hfs) t su(fbls) t h(blfl) t d(hdv) t d(ldd) t h(hfs) t su(fbls) t h(blfl) t su(drbl) t h(bldr) t h(bldr)
s5t8554b/7b 1 chip codec 8 timing diagram (c ontinued ) figure 2. long frame sync timing 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 3 4 5 6 7 8 1 2 3 4 5 6 7 8 bclk x fs x d x bclk r fs r d r t su(bhml) t h(3rd) t d(ldd) t h(hfs) t su(fblk) t h(bldl) t h(bldl) t r(mck) mclk r mclk x t w(mckl) t f(mck) t ck t w(mckh) t sbfm 9 t h(hfs) t su(fbck) t rb t f(bck) t w(bckh) t w(bckl) t ck t d(vd) t d(vd) t d(hdv) t d(vd) 9 t h(3rd) t su(drbl)
1 chip codec s5t8554b/7b 9 transmission characteristics (unless otherwise specified: ta = 0 c to 70 c, v cc = 5v 5%, v bb = - 5v 5%, gnd a = 0v, f = 1.02khz, v in = 0dbm0, transmit input amplifier connected for unity-gain non-inverting.) characteristic symbol test conditions min. typ. max. unit amplitude response receive gain, absolute g v (arx) ta=25 c, v cc =5v, v bb = - 5v input = digital code sequence for 0dbm signal at 1020hz - 0.15 - 0.15 db receive gain, relative to g v (arx) g v (rrx) f = 0hz to 3000hz f = 3300hz f = 3400hz f = 4000hz - 0.15 - 0.35 - 0.7 - 0.15 0.05 0 - 14 db db db db absolute receive gain variation with temperature d g v (arx) / d t ta = 0 c to 70 c - - 0.1 db absolute receive gain variation with supply voltage d g v (arx) / d v v cc =5v 5%, v bb = - 5v 5% - - 0.05 db receive gain variations with level d g v (rxl) sinusoidal test method, reference input pcm code corresponds to an ideally encoded - 10db0 signal pcm level = - 40dbm0 to +3dbm0 pcm level = - 50dbm0 to - 10dbm0 pcm level = - 55dbm0 to - 50dbm0 - 0.2 - 0.4 - 1.2 - 0.2 0.4 1.2 db db db receive output drive level v o (rx) r l = 600 w - 2.5 - 2.5 v absolute level v al norminal 0dbm0 level is 4dbm (600 w ) 0dbm0 - 1.2276 - vrms max overload level v ol (amx) max overload level (3.17dbm0): s5t8554b max overload level (3.14dbm0): s5t8557b - 2.501 - v pk transmit gain, absolute g v (atx) ta = 25 c, v cc = 5v, v bb = - 5v input at gs x = 0dbm0 at 1020hz - 0.15 - 0.15 db transmit gain, relative to g v (arx) g v (rtx) f = 16hz f = 50hz f = 60hz f = 200hz f = 300hz - 3000hz f = 3300hz f = 3400hz f = 4000hz f = 4600hz and up, measure response from 0hz to 4000hz - 1.8 - 0.15 - 0.35 - 0.7 - - 40 - 30 - 26 - 0.1 0.15 0.05 0 - - 14 - 32 db db db db db db db db db db
s5t8554b/7b 1 chip codec 10 transmission characteristics (unless otherwise specified: ta = 0 c to 70 c, v cc = 5v 5%, v bb = - 5v 5%, gnd a = 0v, f = 1.02khz, v in = 0dbm0, transmit input amplifier connected for unity-gain non-inverting.) characteristic symbol test conditions min. typ. max. unit absolute transmit gain variation with temperature d g v(atx) / d t ta = 0 c to 70 c - - 0.1 db absolute transmit gain variation with supply voltage d g v (atx) / d v v cc = 5v 5%, v bb = - 5v 5% - - 0.05 db transmit gain variations with level - sinusoldal test method reference level = - 10dbm0 vf x i + = - 40dbm0 to +3dbm0 vf x + = - 50dbm0 to - 40dbm0 vf x i + = - 55dbm0 to - 50dbm0 - 0.2 - 0.4 - 1.2 - 0.2 0.4 1.2 db db db envelope delay distortion with frequency receive delay, absolute t d (arx) f = 1600hz - 180 200 m s receive delay, relative to t d (arx) t d (rrx) f = 500hz - 1000hz f = 1000hz - 1600hz f = 1600hz - 2600hz f = 2600hz - 2800hz f = 2800hz - 3000hz - 40 - 30 - 25 - 120 70 100 145 90 125 175 m s m s m s m s m s transmit delay, absolute t d (atx) f = 1600hz - 290 315 m s transmit delay, relative to t d (atx) t d (rtx) f = 500hz - 600hz f = 600hz - 800hz f = 800hz - 1000hz f = 1000hz - 1600hz f = 1600hz - 2600hz f = 2600hz - 2800hz f = 2800hz - 3000hz - 195 120 50 20 55 80 130 220 145 75 40 75 105 155 m s m s m s m s m s m s m s noise receive noise, cmessage weighted n rxc pcm code equals alternating positive and negative zero, s5t8554b - 8 11 dbrnc0 receive noise, pmessage weighted n rxp pcm code equals, positive zero, s5t8557b - - 82 - 79 dbm0p transmit noise, cmessage weighted n txc s5t8554b - 12 15 dbrnc0 transmit noise, pmessage weighted n txp s5t8557b - 74 - 67 dbm0p noise, single frequency n sf f = 0khz to 100khz, loop around measurement, vf x i + = 0vrms - - - 53 dbm0 positive power supply rejection, transmit psrr (ptx) vf x i + = 0vrms, v cc = 5.0v dc + 100mvrms f = 0khz - 50khz 40 - - dbc
1 chip codec s5t8554b/7b 11 transmission characteristics (unless otherwise specified: ta = 0 c to 70 c, v cc = 5v 5%, v bb = - 5v 5%, gnd a = 0v, f = 1.02khz, v in = 0dbm0, transmit input amplifier connected for unity-gain non-inverting.) characteristic symbol test conditions min. typ. max. unit negative power supply rejection, transmit psrr (ntx) vf x i + = 0vrms, v bb = - 5.0v dc + 100mvrms f = 0khz - 50khz 40 - - dbc positive power supply rejection, receive psrr (prx) pcm code equals positive zero v cc = 5.0v dc + 100mvrms f = 0hz - 4000hz f = 4khz - 25khz f = 25khz - 50khz 40 40 36 - - dbc db db negative power supply rejection, receive psrr (nrx) pcm code equals positive zero v bb = 5.0v dc + 100mvrms f = 0hz - 4000hz f = 4khz - 25khz f = 25khz - 50khz 40 40 36 - - dbc db db spurious out-of-band signals at the channel output sos loop around measurement, 0dbm0, 300hz - 3400hz input pcm applied to d r , measure individual image signals at vf r o 4600hz - 760hz 7600hz - 8400hz 8400hz - 100,000hz - - - 32 - 40 - 32 db db db distortion signal to total distortion transmit or receive half- channel thd tx thd rx sinusoidal test method level = 3.0dbm0 = 0dbm0 to 30dbm0 = - 40dbm0 xmt rcv = - 55dbm0 xmt rcv 33 26 29 30 14 15 - - dbc dbc dbc dbc dbc dbc single frequency distortion, transmit thd sf (tdo) - - - - 46 db single frequency distortion, receive thd sf (rx) - - - - 46 db intermodulation distortion thd imd loop around measurement, vf x i + = - 4dbm0 to - 21dbm0, two frequencies in the range 300hz - 3400hz - - - 41 db crosstalk transmit to receive crosstalk, 0db0 transmit level ct (tx-rx) f = 300hz - 3400hz d r = steady pcm code - - 90 - 75 db
s5t8554b/7b 1 chip codec 12 transmission characteristics (unless otherwise specified: ta = 0 c to 70 c, v cc = 5v 5%, v bb = - 5v 5%, gnd a = 0v, f = 1.02khz, v in = 0dbm0, transmit input amplifier connected for unity-gain non-inverting.) note: ct (rx-tx) is measured with a - 40dbm0 activating signal applied at vf x i + encoding format at d x output characteristic symbol test conditions min. typ. max. unit receive to transmit crosstalk, 0dbm0 receive level ct (rx-tx) - - - 90 - 70 (note1) db m -law kt8554 a-law kt8557 v in (at gs x ) = + full scale 10000000 10101010 v in (at gs x ) = 0v 11111111 01111111 11010101 01010101 v in (at gs x ) = -full scale 0000000 00101010
1 chip codec s5t8554b/7b 13 application circuit notes: 1. supposing desired line termination impedance r l = 600ohm it is 0dbm = 0.77459vrms 2. t x gain 20 log (r2/r1), r1 + r2 < 100kohm, or the correspondence of 1-chip codec 0dbm 0 = 4dbm. selection of master clock frequency bclkr/clksel s5t8554b s5t8557b clocked 1.536 / 1.544mhz 2.048mhz 0 2.048mhz 1.536 / 1.544mhz 1 (or open) 1.536 / 1.544mhz 2.048mhz vf x i + vf x i - gs x d x fs x s bclk x mclk x v bb gnd vf r o v cc fs r d r bclk r /clksel mclk r /pdn 1 2 3 4 5 6 7 8 16 15 14 11 12 10 9 kt8554/7 r2 to slic from slic r1 r4 r3 pdn r6 fs x/r u-low only clock dr dx +5v -5v 0.1 m f 0.1 m f s5t8554b/7b
s5t8554b/7b 1 chip codec 14 notes

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